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Table 3.
AC Characteristics
Applicable over recommended operating range from V CC = +2.7 to 5.5V, T AC = -40°C to +85°C, CL = 30pF
( unless otherwise noted )
Symbol
f CLK
f CLK
f CLK
Parameter
Async Clock Frequency (V CC Range: +4.5 - 5.5V)
Async Clock Frequency (V CC Range: +2.7 - 3.3V)
Synch Clock Frequency
Clock Duty cycle
Min
1
1
0
40
Max
5
4
1
60
Units
MHZ
MHZ
MHZ
%
t R
t F
t R
t F
t AA
t HD.STA
t SU.STA
t HD.DAT
t SU.DAT
t SU.STO
t DH
t WR
t WR
Rise Time - I/O, RST
Fall Time - I/O, RST
Rise Time - CLK
Fall Time - CLK
Clock Low to Data Out Valid
Start Hold Time
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Stop Set-up Time
Data Out Hold Time
Write Cycle Time (at 25 ° C)
Write Cycle Time (-40° to +85°C)
200
200
10
100
200
20
1
1
9% x period
9% x period
35
5
7
μ S
μ S
μ S
μ S
nS
nS
nS
nS
nS
nS
nS
mS
mS
4.
Device Operation for Synchronous Protocols
CLOCK and DATA TRANSITIONS : The SDA pin is normally pulled high with an external device. Data on the SDA pin
may change only during SCL low time periods (see Figure 5 on page 8). Data changes
during SCL high periods will indicate a start or stop condition as defined below.
START CONDITION :
STOP CONDITION :
ACKNOWLEDGE :
MEMORY RESET :
A high-to-low transition of SDA with SCL high is a start condition which must precede any
other command (see Figure 6 on page 8).
A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the
stop command will place the EEPROM in a standby power mode (see Figure 6 on page 8).
All addresses and data words are serially transmitted to and from the EEPROM in 8-bit
words. The EEPROM sends a zero to acknowledge that it has received each word. This
happens during the ninth clock cycle.
After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by
following these steps:
1.
Clock up to 9 cycles.
6
AT88SC3216C
5014KS–SMEM–08/09
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